Analyzing Memory Bus to Meet with DDR Specifications
The latest technology for serial links and memory interfaces is getting into the multi-gigabit range. We see them adopting multi-level modulations and more advanced data recovery methods. As a result creating a stable and compliant design is more challenging than ever before and standard signal integrity analysis is no longer sufficient.
Keysight is offering a design flow, which gives you all the insights you need. In this webinar series, our experts will cover leading edge applications of Keysight's premier SerDes and Memory simulation platform, PathWave ADS, with respect to Signal Integrity, Power Integrity and EMI simulation and analysis.
Analyzing Memory Bus to Meet with DDR Specifications
April 14, 2022 | 10:00 a.m. PT / 1:00 p.m. ET
With memory getting into the multi-gigabit range, the design margins are tighter due to higher crosstalk between vias and traces. Optimizing your design and testing it against specifications is critical. We will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to design with them.
Relevant Government Agencies
Other Federal Agencies, Federal Government, State & Local Government
Event Type
Webcast
This event has no exhibitor/sponsor opportunities
When
Thu, Apr 14, 2022, 1:00pm
ET
Cost
Complimentary: $ 0.00
Website
Click here to visit event website
Organizer
Keysight Technologies
