Perform Simulation-Based, Virtual Compliance Tests for (LP)DDR

The latest technology for serial links and memory interfaces is getting into the multi-gigabit range. We see them adopting multi-level modulations and more advanced data recovery methods. As a result creating a stable and compliant design is more challenging than ever before and standard signal integrity analysis is no longer sufficient.
Keysight is offering a design flow, which gives you all the insights you need. In this webinar series, our experts will cover leading edge applications of Keysight's premier SerDes and Memory simulation platform, PathWave ADS, with respect to Signal Integrity, Power Integrity and EMI simulation and analysis.

Perform Simulation-Based, Virtual Compliance Tests for (LP)DDR
November 15, 2022 | 10:00 a.m. PT / 1:00 p.m. ET
Due to ever increasing data rates there is less design margin given to memory design engineers. You will have to make sure that your implementation is compliant to specifications. In this webinar, we will walk through the compliance tests and design exploration with several memory standards.

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Tue, Nov 15, 2022, 1:00pm ET

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